exam question and answer (set 2)

Question

Answer1, answer2, answer3, answer4, answer5

university mathematics B

To all WOU friends.....

Here is the pass year exam question

Here is the answer specimen

Good luck in you'll exam......

Any problem please leave a comment.. Thanks you

From
Foong

SR(set-reset) flip flop

The logic gate for flip-flop

The logic gate in SET mode. (double click the image to see how the logic works)

The logic gate in RESET mode ( double click the image to see how the logic works)

An SR(set-reset) Flip Flop is an arrangements of logic gates that maintains a stable output even after the inputs are turned off. This simple flip flop circuit has a set input (S) and a reset input (R). The set input causes the output of 0 (top output) and 1 (bottom output). The reset input causes the opposite to happen (top = 1, bottom =0). Once the outputs are established, the wiring of the circuit is maintained until S or R go high, or power is turned of to the circuit.

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